Most current-generation dynamic random access memories (DRAMs) utilize CMOS technology. Although the term "CMOS" is an acronym for (C)omplementary (M)etal (O)xide (S)emiconductor, the term CMOS is now more loosely applied to any integrated circuit in which both N-channel and P-channel field-effect transistors are used in a complementary fashion. Although CMOS integrated circuit devices are often referred to as "semiconductor" devices, such devices are fabricated from various materials which are either electrically conductive, electrically nonconductive or electrically semiconductive. Silicon, the most commonly used semiconductor material can be made conductive by doping it (introducing an impurity into the silicon crystal structure) with either an element such as boron which has one less valence electron than silicon, or with an element such as phosphorus or arsenic which have one more valence electron than silicon. In the case of boron doping, electron "holes" become the charge carriers and the doped silicon is referred to as positive or P-type silicon. In the case of phosphorus or arsenic doping, the additional electrons become the charge carriers and the doped silicon is referred to as negative or N-type silicon. If a mixture of dopants having opposite conductivity types is used, counter doping will result, and the conductivity type of the most abundant impurity will prevail. Silicon is used either in single-crystal or polycrystalline form. Polycrystalline silicon is referred to hereinafter as "polysilicon" or simply as "poly". Although polysilicon has largely replaced metal for the MOS device gates, the inherently high conductivity of a metal has led many semiconductor manufacturers to create a layer of refractory metal silicide on transistor gates in order to increase device speed.
CMOS DRAM processes begin with a lightly-doped P-type or N-type silicon substrate. Suffice it to be said that, prior to the development of the split-polysilicon CMOS process, fabrication of a CMOS DRAM memory required at least 12 photoresist masking steps to create both N-channel and P-channel transistors and the cell capacitor on a silicon substrate (an additional one or two masks is required if lightly-doped drain design is required for both types of transistors). No attempt is made at siliciding source and drain regions in this process.
A pending U.S. patent application No. 07/427,639, submitted by Tyler A. Lowrey, Randal W. Chance, and Ward D. Parkinson of Micron Technology, Inc. of Boise, Id. provides a detailed description of the heretofore mentioned split-polysilicon CMOS process. By processing N-channel and P-channel devices separately, three photomasking steps can be eliminated in the manufacture of high-performance CMOS circuits. As with the conventional CMOS process, a single polysilicon layer is used to form both N-channel and P-channel gates. However, N-channel devices are formed first, with an expanse of unetched polysilicon left in the future P-channel regions until N-channel processing is complete.
Another copending patent application No. 07/485,029 entitled "Split Polysilicon CMOS Process Incorporating Self-Aligned Silicidation of Conductive Regions" and submitted by Tyler Lowrey, Mark Durcan, Trung Doan, Gordon Haller, and Mark Tuttle (all of Micron Technology, Inc.) builds on the standard split polysilicon CMOS process by incorporating self-aligned silicidation of all conductive regions (i.e., gates, sources and drains of both N-channel and P-channel transistors). This process requires the deposition and anisotropic dry etch of a transistor sidewall spacer oxide layer for each transistor type. The spacers are used not only to offset transistor source/drain implants, but to prevent silicidation of the transistor gate sidewalls. Using this process, both spacer etch steps must be carefully monitored in order to prevent excessive etching of the field isolation oxide and the doped silicon in the active areas which function as the sources and drains for both types of transistors. Any significant removal of this doped silicon will degrade transistor performance, specifically with regard to junction leakage. Hence, poor control over the spacer etches may lead to poor manufacturing yields.